samp/counter/counter_xunit_bench.v in ruby-vpi-9.0.0 vs samp/counter/counter_xunit_bench.v in ruby-vpi-10.0.0

@@ -1,8 +1,5 @@
-/* This is the Verilog side of the bench. */
-
-`include "counter.v"
-
+/* This file is the Verilog side of the bench. */
 module counter_xunit_bench;
 
   // instantiate the design under test
     parameter Size = 5;
     reg  clock;