samp/counter/counter_rspec_proto.rb in ruby-vpi-14.0.0 vs samp/counter/counter_rspec_proto.rb in ruby-vpi-15.0.0

@@ -1,11 +1,13 @@
 # This is a prototype of the design under test.
 
-# When prototyping is enabled, Vpi::simulate invokes this method
-# instead of transferring control to the Verilog simulator.
+# When prototyping is enabled, Vpi::advance_time invokes this
+# method instead of transferring control to the Verilog simulator.
 def Counter.simulate!
-  if reset.intVal == 1
-    count.intVal = 0
-  else
-    count.intVal += 1
+  if clock.posedge?
+    if reset.intVal == 1
+      count.intVal = 0
+    else
+      count.intVal += 1
+    end
   end
 end