lib/ruby-vpi.rb in ruby-vpi-15.0.2 vs lib/ruby-vpi.rb in ruby-vpi-16.0.0

@@ -1,35 +1,26 @@
-=begin
-  Copyright 2006 Suraj N. Kurapati
+# General Ruby-VPI project information and testbench bootstrapping.
+#--
+# Copyright 2006-2007 Suraj N. Kurapati
+# See the file named LICENSE for details.
 
-  This file is part of Ruby-VPI.
-
-  Ruby-VPI is free software; you can redistribute it and/or
-  modify it under the terms of the GNU General Public License
-  as published by the Free Software Foundation; either version 2
-  of the License, or (at your option) any later version.
-
-  Ruby-VPI is distributed in the hope that it will be useful,
-  but WITHOUT ANY WARRANTY; without even the implied warranty of
-  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-  GNU General Public License for more details.
-
-  You should have received a copy of the GNU General Public License
-  along with Ruby-VPI; if not, write to the Free Software Foundation,
-  Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-=end
-
 module RubyVpi
-  # Initializes the bench by setting up code coverage, the interactive debugger, and so on:
+  # Initializes the bench by setting up code coverage, the interactive debugger,
+  # and so on:
+  #
   # 1. loads the design.rb file
   # 2. loads the proto.rb file if prototyping is enabled
   # 3. loads the spec.rb file
   #
-  # aDesignId:: The name of the Ruby object which gives access to the design under test.
+  # aDesignId:: The name of the Ruby object which gives access to the design
+  #             under test.
+  #
   # aSpecFormat:: The name of the format being used by the specification.
-  # aSimulationCycle:: A block that simulates the design under test by, for example, toggling the clock signal.
   #
+  # aSimulationCycle::  A block that simulates the design under test by, for
+  #                     example, toggling the clock signal.
+  #
   def RubyVpi.init_bench aDesignId, aSpecFormat, &aSimulationCycle
     raise ArgumentError, "block must be given" unless block_given?
 
     if caller.find {|s| s =~ /^(.*?)_bench.rb:/}
       testName = $1
@@ -40,11 +31,12 @@
     useDebugger = !(ENV['DEBUG'] || '').empty?
     useCoverage = !(ENV['COVERAGE'] || '').empty?
     usePrototype = !(ENV['PROTOTYPE'] || '').empty?
 
     # set up code coverage analysis
-      # XXX: this is loaded *before* RCov to prevent coverage statistics about it
+      # XXX: this is loaded *before* RCov to prevent coverage statistics about
+      # it
       require 'ruby-vpi/vpi'
 
       if useCoverage
         require 'ruby-vpi/rcov'
 
@@ -123,11 +115,12 @@
         end
 
         Vpi::vpi_printf "#{Config::PROJECT_NAME}: prototype is enabled for test #{testName.inspect}\n"
 
       else
-        # XXX: this completes the handshake, by calling relay_verilog, with pthread_mutex_lock() in relay_main() in the C extension
+        # XXX: this completes the handshake, by calling relay_verilog, with
+        # pthread_mutex_lock() in relay_main() in the C extension
         advance_time
       end
 
     # load the design's specification
       require "#{testName}_spec.rb"
@@ -138,18 +131,19 @@
     PROJECT_ID = 'ruby-vpi'
     PROJECT_NAME = 'Ruby-VPI'
     PROJECT_URL = "http://#{PROJECT_ID}.rubyforge.org"
     WEBSITE_URL = PROJECT_URL + "/doc"
     PROJECT_SUMMARY = "Ruby interface to IEEE 1364-2005 Verilog VPI"
-    PROJECT_DETAIL = "#{PROJECT_NAME} is a #{PROJECT_SUMMARY}. It lets you create complex Verilog test benches easily and wholly in Ruby."
+    PROJECT_DETAIL = "#{PROJECT_NAME} is a #{PROJECT_SUMMARY} and a platform for unit testing, rapid prototyping, and systems integration of Verilog modules through Ruby. It lets you create complex Verilog test benches easily and wholly in Ruby."
 
-    Simulator = Struct.new(:id, :name, :compiler_args, :linker_args)
+    Simulator = Struct.new(:name, :compiler_args, :linker_args)
 
     # List of supported Verilog simulators.
-    SIMULATORS = [
-      Simulator.new(:cver, 'GPL Cver', '-DPRAGMATIC_CVER', ''),
-      Simulator.new(:ivl, 'Icarus Verilog', '-DICARUS_VERILOG', ''),
-      Simulator.new(:vcs, 'Synopsys VCS', '-DSYNOPSYS_VCS', ''),
-      Simulator.new(:vsim, 'Mentor Modelsim', '-DMENTOR_MODELSIM', ''),
-    ]
+    SIMULATORS = {
+      :cver   => Simulator.new('GPL Cver',        '-DPRAGMATIC_CVER',   ''),
+      :ivl    => Simulator.new('Icarus Verilog',  '-DICARUS_VERILOG',   ''),
+      :vcs    => Simulator.new('Synopsys VCS',    '-DSYNOPSYS_VCS',     ''),
+      :vsim   => Simulator.new('Mentor Modelsim', '-DMENTOR_MODELSIM',  ''),
+      :ncsim  => Simulator.new('Cadence NC-Sim',  '-DCADENCE_NCSIM',    ''),
+    }
   end
 end