examples/counter/xUnit/counter_design.rb in ruby-vpi-19.0.0 vs examples/counter/xUnit/counter_design.rb in ruby-vpi-20.0.0

@@ -1,15 +1,16 @@
 
 # Simulates the design under test for one clock cycle.
-def cycle!
-  clock.high!
+def DUT.cycle!
+  clock.t!
   advance_time
-  clock.low!
+
+  clock.f!
   advance_time
 end
 
 # Brings the design under test into a blank state.
-def reset!
-  reset.high!
+def DUT.reset!
+  reset.t!
   cycle!
-  reset.low!
+  reset.f!
 end