doc/readme.html in ruby-vpi-18.0.2 vs doc/readme.html in ruby-vpi-19.0.0
- old
+ new
@@ -1,27 +1,38 @@
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<meta http-equiv="content-type" content="text/html; charset=utf-8"/>
- <link rel="stylesheet" type="text/css" href="common.css" media="screen" />
+ <link rel="stylesheet" type="text/css" href="screen.css" media="screen" />
<link rel="stylesheet" type="text/css" href="print.css" media="print" />
+ <link rel="alternate stylesheet" type="text/css" href="print.css" title="Print Preview" />
<link rel="alternate" type="application/rss+xml" href="http://ruby-vpi.rubyforge.org/doc/rss.xml" title="RSS feed for this project." />
<title>Ruby-VPI: Ruby interface to Verilog VPI</title>
</head>
<body>
- <div id="site-links">
- <a href="readme.html">Home</a>
- · <a href="manual.html">Manual</a>
- · <a href="memo.html">Memo</a>
- · <a href="history.html">History</a>
- <hr style="display: none"/>
- </div>
+ <div id="menu">
+ <h1>Site navigation</h1>
+ <ul id="site-links">
+ <li><a href="readme.html">Home</a></li>
+ <li><a href="manual.html">Manual</a></li>
+ <li><a href="memo.html">Memo</a></li>
+ <li><a href="history.html">History</a></li>
+ </ul>
-
- <div id="body"><div style="float: right">Version 18.0.2</div>
-<h1 style="padding-top: 0">Ruby-VPI</h1>
+
+ <div id="toc">
+ <h1 id="toc-contents">Contents</h1>
+ <ul><li>1 <a id="a-607217228" href="#resources" class="ref">Resources</a><ul><li>1.1 <a id="a-607205968" href="#Records" class="ref">Records</a></li><li>1.2 <a id="a-607208408" href="#Documentation" class="ref">Documentation</a></li><li>1.3 <a id="a-607211248" href="#Facilities" class="ref">Facilities</a></li></ul></li><li>2 <a id="a-607230458" href="#intro.features" class="ref">Features</a><ul><li>2.1 <a id="a-607220078" href="#Portable" class="ref">Portable</a></li><li>2.2 <a id="a-607222628" href="#Agile" class="ref">Agile</a></li><li>2.3 <a id="a-607225228" href="#Powerful" class="ref">Powerful</a></li></ul></li><li>3 <a id="a-607243448" href="#intro.reqs" class="ref">Requirements</a><ul><li>3.1 <a id="a-607233248" href="#Verilog_simulator" class="ref">Verilog simulator</a></li><li>3.2 <a id="a-607235818" href="#Compilers" class="ref">Compilers</a></li><li>3.3 <a id="a-607238348" href="#Libraries" class="ref">Libraries</a></li></ul></li><li>4 <a id="a-607247078" href="#intro.appetizers" class="ref">Appetizers</a></li><li>5 <a id="a-607250138" href="#intro.applications" class="ref">Applications</a></li><li>6 <a id="a-607257618" href="#intro.related-works" class="ref">Related works</a><ul><li>6.1 <a id="a-607253438" href="#intro.related-works.pli" class="ref">Ye olde PLI</a></li></ul></li><li>7 <a id="a-607261148" href="#intro.license" class="ref">License</a></li></ul>
+ </div>
+ </div>
+
+ <div id="body">
+ <hr style="display: none"/>
+
+<h1 style="padding-top: 0">Ruby-VPI <a style="float: right; position: relative; top: -1em; margin-bottom: -1em;" href="history.html#a19.0.0">19.0.0</a></h1>
+
<p><a href="http://www.ruby-lang.org"><img src="images/ruby/logo-reflection.png" alt="Logo of the Ruby programming language" style="margin: 0; margin-left: 2em; margin-bottom: 1em; float: right"/></a></p>
<p>Ruby-VPI is a platform for unit testing, rapid prototyping, and systems integration of Verilog modules through the <a href="http://www.ruby-lang.org">Ruby programming language</a>. It lets you:</p>
@@ -40,23 +51,23 @@
<p>
<hr style="display: none"/>
<div id="resources" class="section">
<h1 class="title">
- <a href="#a-607228958">1</a>
+ <a href="#a-607217228" class="ref">1</a>
Resources
</h1>
<div id="Records" class="paragraph">
<p class="title">Records</p>
<ul>
- <li><a href="history.html#a18.0.2">What’s new</a>
- – release notes for version 18.0.2.
+ <li><a href="history.html#a19.0.0">What’s new</a>
+ – release notes for version 19.0.0.
<ul>
<li><a href="history.html">History</a>
– a record of all release notes.</li>
<li><a type="application/rss+xml" href="http://ruby-vpi.rubyforge.org/doc/rss.xml"><img src="images/feed-icon-28x28.png" alt="RSS feed for release announcements" style="float: right"/></a> <a href="http://ruby-vpi.rubyforge.org/doc/rss.xml">RSS feed</a>
– keep track of new releases at your leisure.</li>
@@ -120,11 +131,11 @@
<p>
<hr style="display: none"/>
<div id="intro.features" class="section">
<h1 class="title">
- <a href="#a-607249798">2</a>
+ <a href="#a-607230458" class="ref">2</a>
Features
</h1>
@@ -132,11 +143,11 @@
<div id="Portable" class="paragraph">
<p class="title">Portable</p>
<ul>
<li>Supports the <em>entire</em> <a href="http://ieeexplore.ieee.org/xpl/standardstoc.jsp?isnumber=33945"><span class="caps">IEEE 1364</span>-2005 Verilog VPI</a> standard.</li>
- <li>Works with all <a href="#intro.reqs">major Verilog simulators</a> available today.</li>
+ <li>Works with all <a href="#intro.reqs" class="ref">major Verilog simulators</a> available today.</li>
<li>Compiled <em>just once</em> during <a href="manual.html#setup.inst">installation</a> and used forever!</li>
</ul>
</div>
@@ -191,11 +202,11 @@
<p>
<hr style="display: none"/>
<div id="intro.reqs" class="section">
<h1 class="title">
- <a href="#a-607272338">3</a>
+ <a href="#a-607243448" class="ref">3</a>
Requirements
</h1>
@@ -221,11 +232,11 @@
</ul>
<ul>
<li><a href="http://www.cadence.com/products/functional_ver/nc-verilog/">Cadence NC-Sim</a>
- – any version that supports the <tt>+loadvpi</tt> option should be acceptable. However, version 05.83-s003 is <em>mostly</em> acceptable because you <strong>will not</strong> be able to <a href="manual.html#problem.ncsim.vpiForceFlag">force values onto wires</a>.</li>
+ – any version that supports the <tt>+loadvpi</tt> option should be acceptable.</li>
</ul>
<ul>
<li><a href="http://www.pragmatic-c.com/gpl-cver/">GPL Cver</a>
@@ -287,13 +298,84 @@
<p>
<hr style="display: none"/>
+ <div id="intro.appetizers" class="section">
+ <h1 class="title">
+ <a href="#a-607247078" class="ref">4</a>
+
+
+
+ Appetizers
+ </h1>
+
+ Here is a tiny sampling of code to whet your appetite. See <a href="manual.html#usage.tutorial">the tutorial</a> for more samples.
+
+
+ <ul>
+ <li>Assign the value 2<sup>2048</sup> to a register:
+ <ul>
+ <li><code class="code">your_register.intVal = <span style="color:#00D; font-weight:bold">2</span> ** <span style="color:#00D; font-weight:bold">2048</span></code></li>
+ <li><code class="code">your_register.put_value <span style="color:#00D; font-weight:bold">2</span> ** <span style="color:#00D; font-weight:bold">2048</span></code></li>
+ </ul></li>
+ </ul>
+
+
+ <ul>
+ <li>Check if all nets in a module are at high impedance:
+ <ul>
+ <li><code class="code">your_module.all_net? { |your_net| your_net.z? }</code></li>
+ <li><pre class="code">
+your_nets = your_module.net_a
+your_nets.all? { |net| net.z? }</pre></li>
+ </ul></li>
+ </ul>
+
+
+ <ul>
+ <li>See a register’s path, width, and location (file & line number):
+ <ul>
+ <li><code class="code">puts your_register</code></li>
+ <li><pre class="code">
+p <span style="color:#A60">:path</span> => your_register.fullName
+p <span style="color:#A60">:width</span> => your_register.size
+p <span style="color:#A60">:file</span> => your_register.fileName
+p <span style="color:#A60">:file</span> => your_register.lineNo</pre></li>
+ </ul></li>
+ </ul>
+
+
+ <ul>
+ <li>Access the first five elements in a memory:
+ <ul>
+ <li><code class="code">your_memory.memoryWord_a.first(<span style="color:#00D; font-weight:bold">5</span>)</code></li>
+ <li><code class="code">your_memory.memoryWord_a[<span style="color:#00D; font-weight:bold">0</span>..<span style="color:#00D; font-weight:bold">4</span>]</code></li>
+ <li><code class="code">your_memory.memoryWord_a[<span style="color:#00D; font-weight:bold">0</span>, <span style="color:#00D; font-weight:bold">5</span>]</code></li>
+ </ul></li>
+ </ul>
+
+
+ <ul>
+ <li>Clear a memory by filling it with zeroes:
+ <ul>
+ <li><code class="code">your_memory.each_memoryWord { |w| w.zero! }</code></li>
+ <li><code class="code">your_memory.each_memoryWord { |w| w.intVal = <span style="color:#00D; font-weight:bold">0</span> }</code></li>
+ <li><code class="code">your_memory.each_memoryWord { |w| w.put_value <span style="color:#00D; font-weight:bold">0</span> }</code></li>
+ </ul></li>
+ </ul>
+
+ </div>
+ </p>
+
+
+ <p>
+ <hr style="display: none"/>
+
<div id="intro.applications" class="section">
<h1 class="title">
- <a href="#a-607276548">4</a>
+ <a href="#a-607250138" class="ref">5</a>
Applications
</h1>
@@ -333,81 +415,62 @@
<p>
<hr style="display: none"/>
- <div id="intro.appetizers" class="section">
+ <div id="intro.related-works" class="section">
<h1 class="title">
- <a href="#a-607279658">5</a>
+ <a href="#a-607257618" class="ref">6</a>
- Appetizers
+ Related works
</h1>
- <p>Here is a tiny sampling of code to whet your appetite. See <a href="manual.html#usage.tutorial">the tutorial</a> for more samples.</p>
-
-
- <ul>
- <li>Assign the value 2<sup>2048</sup> to a register:</li>
+ <ul>
+ <li><a href="http://anvil.sourceforge.net">ANVIL</a> is a C++ interface to VPI.</li>
+ <li><a href="http://teal.sourceforge.net">Teal</a> is a C++ interface to VPI.</li>
+ <li><a href="http://jove.sourceforge.net">JOVE</a> is a Java interface to VPI.</li>
+ <li><a href="http://embedded.eecs.berkeley.edu/Alumni/pinhong/scriptEDA/">ScriptEDA</a> is a Perl, Python, and Tcl interface to VPI.</li>
+ <li><a href="http://rhdl.rubyforge.org">RHDL</a> is a hardware description and verification language based on Ruby.</li>
+ <li><a href="http://myhdl.jandecaluwe.com">MyHDL</a> is a hardware description and verification language based on Python, which features conversion to Verilog and co-simulation.</li>
</ul>
- <blockquote>
- <p><code class="code">your_register.intVal = <span style="color:#00D; font-weight:bold">2</span> ** <span style="color:#00D; font-weight:bold">2048</span></code></p>
- </blockquote>
+ <p>
+ <hr style="display: none"/>
+ <div id="intro.related-works.pli" class="section">
+ <h2 class="title">
+ <a href="#a-607253438" class="ref">6.1</a>
- <ul>
- <li>Check if all nets in a module are at high impedance:</li>
- </ul>
+
+ Ye olde PLI
+ </h2>
- <blockquote>
- <p><code class="code">your_module.all_net? { |net| net.z? }</code></p>
- </blockquote>
+ The following projects utilize the archaic <strong>tf</strong> and <strong>acc</strong> PLI interfaces, which have been officially deprecated in IEEE Std 1364-2005.
<ul>
- <li>See a register’s path, width, and location (file & line number):</li>
+ <li><a href="http://www.nelsim.com">ScriptSim</a> is a Perl, Python, and Tcl/Tk interface to PLI.</li>
+ <li><a href="http://www.veripool.com/verilog-pli.html">Verilog::Pli</a> is a Perl interface to PLI.</li>
</ul>
+ </div>
+ </p>
- <blockquote>
- <p><code class="code">puts your_register</code></p>
- </blockquote>
-
-
- <ul>
- <li>Access the first five elements in a memory:</li>
- </ul>
-
-
- <blockquote>
- <p><code class="code">your_memory.memoryWord_a[<span style="color:#00D; font-weight:bold">0</span>..<span style="color:#00D; font-weight:bold">4</span>]</code></p>
- </blockquote>
-
-
- <ul>
- <li>Clear a memory by filling it with zeroes:</li>
- </ul>
-
-
- <blockquote>
- <p><code class="code">your_memory.each_memoryWord {|w| w.intVal = <span style="color:#00D; font-weight:bold">0</span>}</code></p>
- </blockquote>
-
</div>
</p>
<p>
<hr style="display: none"/>
<div id="intro.license" class="section">
<h1 class="title">
- <a href="#a-607284018">6</a>
+ <a href="#a-607261148" class="ref">7</a>
License
</h1>
@@ -442,56 +505,11 @@
<span class="caps">IN AN ACTION OF CONTRACT</span>, TORT <span class="caps">OR OTHERWISE</span>, ARISING FROM, OUT <span class="caps">OF OR IN</span>
<span class="caps">CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE</span>.</p>
</div>
</p>
-
-
- <p>
- <hr style="display: none"/>
-
- <div id="intro.related-works" class="section">
- <h1 class="title">
- <a href="#a-607290678">7</a>
-
-
-
- Related works
- </h1>
-
- <ul>
- <li><a href="http://jove.sourceforge.net">JOVE</a> is a Java interface to VPI.</li>
- <li><a href="http://teal.sourceforge.net">Teal</a> is a C++ interface to VPI.</li>
- <li><a href="http://embedded.eecs.berkeley.edu/Alumni/pinhong/scriptEDA/">ScriptEDA</a> is a Perl, Python, and Tcl interface to VPI.</li>
- <li><a href="http://rhdl.rubyforge.org">RHDL</a> is a hardware description and verification language based on Ruby.</li>
- <li><a href="http://myhdl.jandecaluwe.com">MyHDL</a> is a hardware description and verification language based on Python, which features conversion to Verilog and co-simulation.</li>
- </ul>
-
-
- <p>
- <hr style="display: none"/>
-
- <div id="intro.related-works.pli" class="section">
- <h2 class="title">
- <a href="#a-607287248">7.1</a>
-
-
-
- Ye olde PLI
- </h2>
-
- The following projects utilize the archaic <strong>tf</strong> and <strong>acc</strong> PLI interfaces, which have been officially deprecated in IEEE Std 1364-2005.
-
-
- <ul>
- <li><a href="http://www.nelsim.com">ScriptSim</a> is a Perl, Python, and Tcl/Tk interface to PLI.</li>
- <li><a href="http://www.veripool.com/verilog-pli.html">Verilog::Pli</a> is a Perl interface to PLI.</li>
- </ul>
-
+ <br/>
+ <hr/>
+ This website is maintained by Suraj N. Kurapati (SNK at GNA dot ORG). This particular webpage was last updated on Mon Aug 27 19:26:45 -0700 2007.
</div>
- </p>
-
- </div>
- </p></div>
-
- </body>
+ </body>
</html>