bin/generate_test_tpl/proto.rb in ruby-vpi-9.0.0 vs bin/generate_test_tpl/proto.rb in ruby-vpi-10.0.0

@@ -1,10 +1,12 @@
-# A prototype of the design under test.
-class <%= aOutputInfo.protoClassName %> < <%= aOutputInfo.designClassName %>
+# This is a prototype of the design under test.
+class << <%= aOutputInfo.designClassName %>
+  # When prototyping is enabled, this method is invoked
+  # instead of Vpi::relay_verilog to simulate the design.
   def simulate!
     # discard old outputs
 <% aModuleInfo.ports.reject { |p| p.input? }.each do |port| %>
-      @<%= port.name %>.hexStrVal = 'x'
+      <%= port.name %>.hexStrVal = 'x'
 <% end %>
 
     # process new inputs
 
     # produce new outputs