bin/generate_test_tpl/proto.rb in ruby-vpi-13.0.0 vs bin/generate_test_tpl/proto.rb in ruby-vpi-14.0.0

@@ -1,7 +1,7 @@
 # This is a prototype of the design under test.
 
-# When prototyping is enabled, relay_verilog invokes this method
+# When prototyping is enabled, Vpi::simulate invokes this method
 # instead of transferring control to the Verilog simulator.
 def <%= aOutputInfo.designClassName %>.simulate!
   # discard old outputs
 <% aModuleInfo.ports.reject { |p| p.input? }.each do |port| %>
     <%= port.name %>.hexStrVal = 'x'