proto.rb in ruby-vpi-11.0.0

- old
+ new

@@ -1,15 +1,14 @@
 # This is a prototype of the design under test.
-class << <%= aOutputInfo.designClassName %>
-  # When prototyping is enabled, this method is invoked
-  # instead of Vpi::relay_verilog to simulate the design.
-  def simulate!
-    # discard old outputs
+
+# When prototyping is enabled, relay_verilog invokes this method
+# instead of transferring control to the Verilog simulator.
+def <%= aOutputInfo.designClassName %>.simulate!
+  # discard old outputs
 <% aModuleInfo.ports.reject { |p| p.input? }.each do |port| %>
-      <%= port.name %>.hexStrVal = 'x'
+    <%= port.name %>.hexStrVal = 'x'
 <% end %>
 
-    # process new inputs
+  # process new inputs
 
-    # produce new outputs
-  end
+  # produce new outputs
 end