bin/generate_test_tpl/design.rb in ruby-vpi-9.0.0 vs bin/generate_test_tpl/design.rb in ruby-vpi-10.0.0

@@ -1,26 +1,12 @@
-# An interface to the design under test.
-class <%= aOutputInfo.designClassName %>
-  include Vpi
-
-<% (aParseInfo.constants + aModuleInfo.parameters).each do |var| %>
-  <%= var.name.to_ruby_const_name %> = <%= var.value.verilog_to_ruby %>
+# This is a Ruby interface to the design under test.
+<% aParseInfo.constants.each do |var| %>
+<%= var.name.to_ruby_const_name %> = <%= var.value.verilog_to_ruby %>
 <% end %>
 
-  attr_reader <%=
-    aModuleInfo.ports.map do |port|
-      ":#{port.name}"
-    end.join(', ')
-  %>
-
-  def initialize
-<% aModuleInfo.ports.each do |port| %>
-    @<%= port.name %> = vpi_handle_by_name("<%= aOutputInfo.verilogBenchName %>.<%= port.name %>", nil)
-<% end %>
-  end
-
+class << <%= aOutputInfo.designClassName %>
   def reset!
-<% aModuleInfo.ports.select { |p| p.input? }[1..-1].each do |port| %>
-    @<%= port.name %>.hexStrVal = 'x'
+<% aModuleInfo.ports.select { |p| p.input? }[1..-1].each do |port| # using [1..] because the first signal is the clock %>
+    <%= port.name %>.hexStrVal = 'x'
 <% end %>
   end
 end