bin/generate_test_tpl/design.rb in ruby-vpi-10.0.0 vs bin/generate_test_tpl/design.rb in ruby-vpi-11.0.0

@@ -1,12 +1,11 @@
 # This is a Ruby interface to the design under test.
 <% aParseInfo.constants.each do |var| %>
 <%= var.name.to_ruby_const_name %> = <%= var.value.verilog_to_ruby %>
 <% end %>
 
-class << <%= aOutputInfo.designClassName %>
-  def reset!
+# This method resets the design under test.
+def <%= aOutputInfo.designClassName %>.reset!
 <% aModuleInfo.ports.select { |p| p.input? }[1..-1].each do |port| # using [1..] because the first signal is the clock %>
-    <%= port.name %>.hexStrVal = 'x'
+  <%= port.name %>.hexStrVal = 'x'
 <% end %>
-  end
 end