bin/generate_test_tpl/bench.rb in ruby-vpi-13.0.0 vs bin/generate_test_tpl/bench.rb in ruby-vpi-14.0.0

@@ -1,6 +1,89 @@
+<%
+  clock = aOutputInfo.designClassName + '.' + aModuleInfo.ports.first.name
+%>
 # This file is the Ruby side of the bench.
 
 require 'rubygems'
 require 'ruby-vpi'
 
-RubyVpi.init_bench :<%= aOutputInfo.designClassName %>, :<%= aOutputInfo.specFormat %>
+RubyVpi.init_bench :<%= aOutputInfo.designClassName %>, :<%= aOutputInfo.specFormat %> do
+  ##
+  # This block is executed whenever Vpi::simulate is invoked.
+  #
+  # It simulates the design under test. This is typically done
+  # by toggling the clock signal, as demonstrated below.
+  ##
+
+  ##
+  # We are currently here (marked by the ! signs):
+  #
+  #    !
+  #    !
+  #    ! ____      ____      ____      ____
+  # ___!/    \____/    \____/    \____/    \
+  #    !
+  #    !
+  #
+  ##
+
+  <%= clock %>.intVal = 1
+
+  ##
+  # After setting the clock signal to high, we are here:
+  #
+  #      !
+  #      !
+  #      !____      ____      ____      ____
+  # ____/!    \____/    \____/    \____/    \
+  #      !
+  #      !
+  #
+  ##
+
+  advance_time
+
+  ##
+  # After advancing the time, we are here:
+  #
+  #          !
+  #          !
+  #      ____!      ____      ____      ____
+  # ____/    !\____/    \____/    \____/    \
+  #          !
+  #          !
+  #
+  ##
+
+  <%= clock %>.intVal = 0
+
+  ##
+  # After setting the clock signal to low, we are here:
+  #
+  #           !
+  #           !
+  #      ____ !     ____      ____      ____
+  # ____/    \!____/    \____/    \____/    \
+  #           !
+  #           !
+  #
+  ##
+
+  advance_time
+
+  ##
+  # After advancing the time, we are here:
+  #
+  #
+  #               !
+  #               !
+  #      ____     ! ____      ____      ____
+  # ____/    \____!/    \____/    \____/    \
+  #               !
+  #               !
+  #
+  ##
+
+  ##
+  # This process repeats when Vpi::simulate is invoked again.
+  ##
+end