bin/generate/proto.rb in ruby-vpi-18.0.2 vs bin/generate/proto.rb in ruby-vpi-19.0.0

@@ -1,13 +1,18 @@
-# Ruby prototype of the design under test's Verilog implementation.
-def feign!
-  if <%= aModuleInfo.clock_port.name rescue "YOUR_CLOCK_SIGNAL_HERE" %>.posedge?
-    # discard old outputs
-    <% aModuleInfo.output_ports.each do |port| %>
-      <%= port.name %>.x!
-    <% end %>
+always do
+  wait until <%= aModuleInfo.clock_port.name rescue "YOUR_CLOCK_SIGNAL_HERE" %>.posedge?
 
-    # process new inputs
+  # discard old outputs
+  <% aModuleInfo.output_ports.each do |port| %>
+    <%= port.name %>.x!
+  <% end %>
 
-    # produce new outputs
-  end
+  # process new inputs
+  <% aModuleInfo.input_ports.each do |port| %>
+    # some_interesting_process( <%= port.name %> )
+  <% end %>
+
+  # produce new outputs
+  <% aModuleInfo.output_ports.each do |port| %>
+    # <%= port.name %> = some interesting output
+  <% end %>
 end