metasm/cpu/arm64/main.rb in metasm-1.0.3 vs metasm/cpu/arm64/main.rb in metasm-1.0.4

@@ -22,11 +22,11 @@
 			@sz = sz
 		end
 
 		Sym = @i_to_s[64].inject({}) { |h, (k, v)| h.update k => v.to_sym }
 
-		def symbolic
+		def symbolic(di=nil)
 			if @sz == 64
 				Sym[@i]
 			else
 				Expression[Sym[@i], :&, 0xffffffff]
 			end
@@ -39,11 +39,11 @@
 			@reg = reg
 			@mode = mode
 			@shift = shift
 		end
 
-		def symbolic
+		def symbolic(di=nil)
 			sym = @reg.symbolic
 			if shift != 0
 				case @mode
 				when :lsl; Expression[sym, :<<, shift]
 				when :lsr; Expression[sym, :>>, shift]
@@ -57,29 +57,29 @@
 	class RegCC
 		attr_accessor :cc
 		def initialize(cc)
 			@cc = cc
 		end
-		def symbolic
+		def symbolic(di=nil)
 			0
 		end
 	end
 
 	class Memref
 		attr_accessor :base, :index, :scale, :offset, :sz, :incr
 		def initialize(base, index, scale, offset, sz, incr=nil)
 			@base, @index, @scale, @offset, @sz, @incr = base, index, scale, offset, sz, incr
 		end
 
-		def symbolic(orig=nil)
+		def symbolic(di=nil)
 			o = Expression[@base.symbolic]
 			if @index
 				si = @index.symbolic
 				si = Expression[@scale, :*, @index] if @scale != 1
 				o = Expression[o, :+, si]
 			end
 			o = Expression[o, :+, @offset] if @offset and @incr != :post
-			Indirection[o.reduce, @sz, orig]
+			Indirection[o.reduce, @sz, (di.address if di)]
 		end
 	end
 
 	class RegList
 		attr_accessor :list