vendor/assets/javascripts/highlight_js/languages/vhdl.js in highlight_js-rails-0.0.2 vs vendor/assets/javascripts/highlight_js/languages/vhdl.js in highlight_js-rails-7.1.0

- old
+ new

@@ -1,30 +1,51 @@ /* Language: VHDL +Author: Igor Kalnitsky <igor@kalnitsky.org> +Contributors: Daniel C.K. Kho <daniel.kho@gmail.com> Description: VHDL is a hardware description language used in electronic design automation to describe digital and mixed-signal systems. -Author: Igor Kalnitsky <igor.kalnitsky@gmail.com> -Website: http://kalnitsky.org.ua/ */ -hljs.LANGUAGES.vhdl = { - case_insensitive: true, - defaultMode: { - keywords: { - 'keyword': { 'abs': 1, 'access': 1, 'after': 1, 'alias': 1, 'all': 1, 'and': 1, 'architecture': 2, 'array': 1, 'assert': 1, 'attribute': 1, 'begin': 1, 'block': 1, 'body': 1, 'buffer': 1, 'bus': 1, 'case': 1, 'component': 2, 'configuration': 1, 'constant': 1, 'disconnect': 2, 'downto': 2, 'else': 1, 'elsif': 1, 'end': 1, 'entity': 2, 'exit': 1, 'file': 1, 'for': 1, 'function': 1, 'generate': 2, 'generic': 2, 'group': 1, 'guarded': 2, 'if': 0, 'impure': 2, 'in': 1, 'inertial': 1, 'inout': 1, 'is': 1, 'label': 1, 'library': 1, 'linkage': 1, 'literal': 1, 'loop': 1, 'map': 1, 'mod': 1, 'nand': 1, 'new': 1, 'next': 1, 'nor': 1, 'not': 1, 'null': 1, 'of': 1, 'on': 1, 'open': 1, 'or': 1, 'others': 1, 'out': 1, 'package': 1, 'port': 2, 'postponed': 1, 'procedure': 1, 'process': 1, 'pure': 2, 'range': 1, 'record': 1, 'register': 1, 'reject': 1, 'return': 1, 'rol': 1, 'ror': 1, 'select': 1, 'severity': 1, 'signal': 1, 'shared': 1, 'sla': 1, 'sli': 1, 'sra': 1, 'srl': 1, 'subtype': 2, 'then': 1, 'to': 1, 'transport': 1, 'type': 1, 'units': 1, 'until': 1, 'use': 1, 'variable': 1, 'wait': 1, 'when': 1, 'while': 1, 'with': 1, 'xnor': 1, 'xor': 1}, - 'type': { 'boolean': 1, 'bit': 1, 'character': 1, 'severity_level': 2, 'integer': 1, 'time': 1, 'delay_length': 2, 'natural': 1, 'positive': 1, 'string': 1, 'bit_vector': 2, 'file_open_kind': 2, 'file_open_status': 2, 'std_ulogic': 2, 'std_ulogic_vector': 2, 'std_logic': 2, 'std_logic_vector': 2 } - }, - contains: [ - { - className: 'comment', - begin: '--', end: '$' +hljs.LANGUAGES['vhdl'] = function(hljs) { + return { + case_insensitive: true, + defaultMode: { + keywords: { + keyword: + 'abs access after alias all and architecture array assert attribute begin block ' + + 'body buffer bus case component configuration constant context cover disconnect ' + + 'downto default else elsif end entity exit fairness file for force function generate ' + + 'generic group guarded if impure in inertial inout is label library linkage literal ' + + 'loop map mod nand new next nor not null of on open or others out package port ' + + 'postponed procedure process property protected pure range record register reject ' + + 'release rem report restrict restrict_guarantee return rol ror select sequence ' + + 'severity shared signal sla sll sra srl strong subtype then to transport type ' + + 'unaffected units until use variable vmode vprop vunit wait when while with xnor xor', + typename: + 'boolean bit character severity_level integer time delay_length natural positive ' + + 'string bit_vector file_open_kind file_open_status std_ulogic std_ulogic_vector ' + + 'std_logic std_logic_vector unsigned signed boolean_vector integer_vector ' + + 'real_vector time_vector' }, - hljs.QUOTE_STRING_MODE, - hljs.C_NUMBER_MODE, - { - className: 'literal', - begin: '\'(U|X|0|1|Z|W|L|H|-)', end: '\'', - contains: [hljs.BACKSLASH_ESCAPE], - relevance: 5 - } - ] - } -}; + illegal: '{', + contains: [ + hljs.C_BLOCK_COMMENT_MODE, // VHDL-2008 block commenting. + { + className: 'comment', + begin: '--', end: '$' + }, + hljs.QUOTE_STRING_MODE, + hljs.C_NUMBER_MODE, + { + className: 'literal', + begin: '\'(U|X|0|1|Z|W|L|H|-)\'', + contains: [hljs.BACKSLASH_ESCAPE] + }, + { + className: 'attribute', + begin: '\'[A-Za-z](_?[A-Za-z0-9])*', + contains: [hljs.BACKSLASH_ESCAPE] + } + ] + } // defaultMode + } // return; +}(hljs);