lib/HDLRuby/hdr_samples/with_channel.rb in HDLRuby-2.3.2 vs lib/HDLRuby/hdr_samples/with_channel.rb in HDLRuby-2.3.3
- old
+ new
@@ -61,24 +61,26 @@
# A system writing indefinitely to a channel.
+# Checking usage of channel without declaring a port.
system :producer8 do |channel|
- # puts "channel=#{channel}"
+ # puts "channel=#{channel}, channel methods=#{channel.methods}"
# Inputs of the producer: clock and reset.
input :clk, :rst
- # Instantiate the channel ports
- channel.output :ch
+ # # Instantiate the channel ports
+ # channel.output :ch
# Inner 8-bit counter for generating values.
[8].inner :counter
# The value production process
par(clk.posedge) do
hif(rst) { counter <= 0 }
helse do
- ch.write(counter) { counter <= counter + 1 }
+ # ch.write(counter) { counter <= counter + 1 }
+ channel.write(counter) { counter <= counter + 1 }
end
end
end
# A system reading indefinitely from a channel.
@@ -94,22 +96,61 @@
par(clk.posedge) do
ch.read(buf)
end
end
+# A system reading indefinitely from a channel.
+# Version without port declaration.
+system :consummer16 do |channel|
+ # Input of the consummer: a clock is enough.
+ input :clk
+ # # Instantiate the channel ports
+ # channel.input :ch
+ # Inner buffer for storing the cunsummed value.
+ [16].inner :buf
+ # The value consumption process
+ par(clk.posedge) do
+ # ch.read(buf)
+ channel.read(buf)
+ end
+end
+
+
# A system testing the handshaker.
system :hs_test do
input :clk,:rst
- # Declares the handshaker
- handshaker([8]).(:hs)
+ # Declares two handshakers
+ handshaker([8]).(:hs0)
+ handshaker([16]).(:hs1)
# # Sets the reset.
# par(rst.posedge) { hs.reset }
+
+ # For the first handshake
# Instantiate the producer.
- producer8(hs).(:producerI).(clk,rst)
+ producer8(hs0).(:producerI).(clk,rst)
# Instantiate the consummer.
- consummer8(hs).(:consummerI).(clk)
+ consummer8(hs0).(:consummerI).(clk)
+
+ # For the second handshaker
+
+ # Instantiatethe consummer.
+ consummer16(hs1).(:consummer2I).(clk)
+
+ # Produce from within.
+ [16].inner :counter
+
+ # hs1.output :port
+
+ par(clk.posedge) do
+ hif(rst) { counter <= 0 }
+ helse do
+ # port.write(counter) { counter <= counter + 1 }
+ hs1.write(counter) { counter <= counter + 1 }
+ end
+ end
+
end