Contents

# Ruby prototype of the design under test's Verilog implementation.
def feign!
  if clock.posedge?
    if reset.high?
      count.intVal = 0
    else
      count.intVal += 1
    end
  end
end

Version data entries

8 entries across 4 versions & 1 rubygems

Version	Path
ruby-vpi-17.0.0	samp/counter/xUnit/counter_proto.rb
ruby-vpi-18.0.0	samp/counter/RSpec/counter_proto.rb
ruby-vpi-18.0.0	samp/counter/xUnit/counter_proto.rb
ruby-vpi-17.0.0	samp/counter/RSpec/counter_proto.rb
ruby-vpi-18.0.2	samp/counter/xUnit/counter_proto.rb
ruby-vpi-18.0.1	samp/counter/xUnit/counter_proto.rb
ruby-vpi-18.0.1	samp/counter/RSpec/counter_proto.rb
ruby-vpi-18.0.2	samp/counter/RSpec/counter_proto.rb