text/x-verilog-src
*.v
//
/*
*/
`
celldefine
default_nettype
define
else
elsif
endcelldefine
endif
ifdef
ifndef
include
line
nounconnected_drive
resetall
timescale
unconnected_drive
undef
always
assign
attribute
begin
case
casex
casez
deassign
default
defparam
disable
edge
else
endattribute
endcase
endfunction
endmodule
endprimitive
endspecify
endtable
endtask
end
force
forever
fork
for
function
highz0
highz1
if
ifnone
initial
join
large
macromodule
medium
module
negedge
posedge
primitive
pull0
pull1
release
repeat
signed
small
specify
specparam
strength
strong0
strong1
table
task
unsigned
wait
weak0
weak1
while
and
buf
bufif0
bufif1
cmos
nand
nmos
nor
not
notif0
notif1
or
pmos
pullup
pulldown
rcmos
rnmos
rpmos
rtran
rtranif0
rtranif1
tran
tranif0
tranif1
xnor
xor
event
inout
input
integer
output
parameter
reg
real
realtime
scalared
supply0
supply1
time
tri
tri0
tri1
triand
trior
trireg
vectored
wand
wire
wor
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[1-9][0-9]*'[oO][0-7_xXzZ?]+
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[1-9][0-9]*'[dD][0-9_xXzZ?]+
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[1-9][0-9]*'[hH][0-9a-fA-F_xXzZ?]+
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