Class | VerilogParser::Module |
In: |
lib/ruby-vpi/verilog_parser.rb
|
Parent: | Object |
body | [R] | |
clock_port | [R] | |
decl | [R] | |
input_ports | [R] | |
name | [R] | |
output_ports | [R] | |
ports | [R] | |
reset_port | [R] |