Contents

# Simulates the design under test for one clock cycle.
def DUT.cycle!
  advance_time
end

# Brings the design under test into a blank state.
def DUT.reset!
  register.each_memoryWord do |word|
    word.x!
  end
end

Version data entries

3 entries across 3 versions & 1 rubygems

Version	Path
ruby-vpi-20.0.0	examples/register_file/register_file_design.rb
ruby-vpi-21.0.0	examples/register_file/register_file_design.rb
ruby-vpi-21.1.0	examples/register_file/register_file_design.rb