# File lib/ruby-vpi/verilog_parser.rb, line 36
36:     def initialize aDecl
37:       @decl = aDecl.strip
38: 
39:       @decl =~ %r{module\s+(\w+)\s*(?:\#\((.*?)\))?\s*\((.*?)\)\s*;}m
40:       @name, paramDecls, portDecls = $1, $2, $3
41: 
42:       @parameters =
43:         if paramDecls =~ %r{\bparameter\b(.*)$}
44:           $1.split(',').map! do |decl|
45:             Parameter.new decl
46:           end
47:         else
48:           []
49:         end
50: 
51:       @ports = portDecls.split(',').map! do |decl|
52:         Port.new decl
53:       end
54:     end