Contents

# This is a Ruby interface to the design under test.

WIDTH = 32
DATABITS = 7
OP_NOP = 0
OP_ADD = 1
OP_SUB = 2
OP_MULT = 3
OPERATIONS = (OP_NOP..OP_MULT).to_a

# Number of cycles needed to reset this design.
RESET_DELAY = 5

# This method resets the design under test.
def Hw5_unit.reset!
  reset.hexStrVal = 'x'
  in_databits.hexStrVal = 'x'
  a.hexStrVal = 'x'
  b.hexStrVal = 'x'
  in_op.hexStrVal = 'x'


  reset.intVal = 1

  RESET_DELAY.times do
    relay_verilog
  end

  reset.intVal = 0
end


# Represents an ALU operation.
class Operation
  attr_accessor :type, :tag, :arg1, :arg2, :stage, :result

  def initialize(type, tag, arg1 = 0, arg2 = 0)
    raise ArgumentError unless OPERATIONS.include? type

    @type = type
    @tag = tag
    @arg1 = arg1
    @arg2 = arg2

    @stage = 0
  end

  # Computes the result of this operation.
  def compute
    case @type
      when OP_ADD
        @arg1 + @arg2

      when OP_SUB
        @arg1 - @arg2

      when OP_MULT
        @arg1 * @arg2

      when OP_NOP
        nil

      else
        raise
    end
  end

  def compute!
    @result = compute
  end
end

Version data entries

6 entries across 6 versions & 1 rubygems

Version	Path
ruby-vpi-11.0.0	samp/pipelined_alu/hw5_unit_test_design.rb
ruby-vpi-11.1.1	samp/pipelined_alu/hw5_unit_test_design.rb
ruby-vpi-11.1.0	samp/pipelined_alu/hw5_unit_test_design.rb
ruby-vpi-12.0.0	samp/pipelined_alu/hw5_unit_test_design.rb
ruby-vpi-12.0.1	samp/pipelined_alu/hw5_unit_test_design.rb
ruby-vpi-12.0.2	samp/pipelined_alu/hw5_unit_test_design.rb