Contents

# Ruby prototype of the design under test's Verilog implementation.
def feign!
  if <%= aModuleInfo.clock_port.name rescue "YOUR_CLOCK_SIGNAL_HERE" %>.posedge?
    # discard old outputs
    <% aModuleInfo.output_ports.each do |port| %>
      <%= port.name %>.x!
    <% end %>

    # process new inputs

    # produce new outputs
  end
end

Version data entries

4 entries across 4 versions & 1 rubygems

Version	Path
ruby-vpi-17.0.0	bin/generate/proto.rb
ruby-vpi-18.0.0	bin/generate/proto.rb
ruby-vpi-18.0.1	bin/generate/proto.rb
ruby-vpi-18.0.2	bin/generate/proto.rb