Contents

#Syntax for sources.rb

add design   chip, :env => ['asic_rtl', 'asic_gate', 'fpga_rtl']
add design   [basic_vhdl, chip], :except => {:env => ['asic']}
#add design chip_tb, :path => '/some/absolute/path'
#add testbench chip_tb, :path => '/some/absolute/path'

Version data entries

5 entries across 5 versions & 1 rubygems

Version	Path
ecic-0.2.2	notes.txt
ecic-0.2.1	notes.txt
ecic-0.2.0	notes.txt
ecic-0.1.0	notes.txt
ecic-0.0.1	notes.txt