Contents

# Simulates the design under test for one clock cycle.
def DUT.cycle!
  clock.t!
  advance_time

  clock.f!
  advance_time
end

# Brings the design under test into a blank state.
def DUT.reset!
  reset.t!
  cycle!
  reset.f!
end

Version data entries

3 entries across 3 versions & 1 rubygems

Version	Path
ruby-vpi-20.0.0	examples/counter/RSpec/counter_design.rb
ruby-vpi-21.1.0	examples/counter/RSpec/counter_design.rb
ruby-vpi-21.0.0	examples/counter/RSpec/counter_design.rb