// Copyright 2010 the V8 project authors. All rights reserved.
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// modification, are permitted provided that the following conditions are
// met:
//
//     * Redistributions of source code must retain the above copyright
//       notice, this list of conditions and the following disclaimer.
//     * Redistributions in binary form must reproduce the above
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//       with the distribution.
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//       from this software without specific prior written permission.
//
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// CPU specific code for arm independent of OS goes here.

#include <sys/syscall.h>
#include <unistd.h>

#ifdef __mips
#include <asm/cachectl.h>
#endif  // #ifdef __mips

#include "v8.h"

#if defined(V8_TARGET_ARCH_MIPS)

#include "cpu.h"

namespace v8 {
namespace internal {

void CPU::Setup() {
  // Nothing to do.
}

void CPU::FlushICache(void* start, size_t size) {
#ifdef __mips
  int res;

  // See http://www.linux-mips.org/wiki/Cacheflush_Syscall
  res = syscall(__NR_cacheflush, start, size, ICACHE);

  if (res) {
    V8_Fatal(__FILE__, __LINE__, "Failed to flush the instruction cache");
  }

#endif    // #ifdef __mips
}


void CPU::DebugBreak() {
#ifdef __mips
  asm volatile("break");
#endif  // #ifdef __mips
}

} }  // namespace v8::internal

#endif  // V8_TARGET_ARCH_MIPS