Contents

// This file is the Verilog side of the bench.
module counter_rspec_bench;
  parameter Size = 5;
  reg  clock;
  reg  reset;
  wire [Size - 1 : 0] count;

  counter #(.Size(Size)) counter_rspec_bench_design(.clock(clock), .reset(reset), .count(count));
endmodule

Version data entries

6 entries across 6 versions & 1 rubygems

Version	Path
ruby-vpi-14.0.0	samp/counter/counter_rspec_bench.v
ruby-vpi-15.0.0	samp/counter/counter_rspec_bench.v
ruby-vpi-15.0.1	samp/counter/counter_rspec_bench.v
ruby-vpi-15.0.2	samp/counter/counter_rspec_bench.v
ruby-vpi-16.0.1	samp/counter/counter_rspec_bench.v
ruby-vpi-16.0.0	samp/counter/counter_rspec_bench.v