1   Welcome to Ruby-VPI

Ruby-VPI is a Ruby interface to IEEE 1364-2005 Verilog VPI. It lets you create complex Verilog test benches easily and wholly in Ruby.

1.1   Features

1.1.1   Portable

• Supports the entire IEEE Std 1364-2005 VPI standard.

• Works with all major Verilog simulators available today.
  • Compiled just once during installation and used forever!

1.1.2   Agile

• Enables agile practices such as
  • test-driven development
  • behavior-driven development
  • rapid prototyping for design exploration

• Eliminates unneccesary work:
  • Specifications are readable, portable, and executable.
  • The automated test generator helps you accomodate design changes with minimal effort.
  • There is absolutely no compiling!

1.1.3   Powerful

• Inherits the power and elegance of Ruby:
  • Unlimited length integers
  • Regular expressions
  • Multi-threading
  • System calls and I/O
  • ad infinitum

• Uses ruby-debug for interactive debugging.
• Uses rcov for test coverage analysis and report generation.

1.1.4   Free

• Gives you the freedom to study, modify, and distribute this software, in accordance with the GNU General Public License.

1.2   Applications

Here is a modest sampling of tasks that Ruby-VPI can be used to perform.

• From the second edition of The Verilog PLI Handbook:
  • C language bus-functional models
  • Reading test vector files
  • Delay calculation
  • Custom output displays
  • Co-simulation
  • Design debug utilities
  • Simulation analysis

• Adapted from Pin Hong’s observations:
  • Writing hardware models in Ruby
  • Dumping or processing netlist data from Verilog database
  • Dumping or processing simulation data
  • Feeding dynamic simulation stimuli
  • Back-annotating delay information
  • Interactive logic simulation
  • Building a distributed simulation

1.3   Appetizers

Here is a modest sampling of code to whet your appetite.

• Assign the value 2²⁰⁴⁸ to a register:

some_register.intVal = 2 ** 2048

• Check if all nets in a module are at high impedance:

some_module.all_net? { |net| net.z? }

• See a register’s path, width, and location (file & line number):

puts some_register

• Simulate fifteen clock cycles:

15.times { simulate }