Generates Ruby-VPI tests from Verilog 2001 module declarations.
- The standard input stream is read if no input files are specified.
- The first input signal in a module’s declaration is assumed to be the
clocking signal.
Progress indicators
module: | A Verilog module has been identified.
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create: | A file is being created because it does not exist.
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skip: | A file is being skipped because it is already up to date.
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update: | A file will be updated because it is out of date. A text merging tool (see
MERGER) will be launched to transfer content from the old file (*.old) and
the new file (*.new) to the out of date file. If a text merging tool is not
specified, then you will have to do the merging by hand.
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Environment variables
MERGER: | A command that invokes a text merging tool with three arguments: (1) old
file, (2) new file, (3) output file. The tool’s output should be
written to the output file.
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Required files
ruby-vpi/verilog_parser
fileutils
digest/md5
ruby-vpi/erb
optparse
ruby-vpi/rdoc