Contents

# This is a Ruby interface to the design under test.

# This method resets the design under test.
def Counter.reset!
  # assert the reset signal for two clock cycles
  reset.intVal = 1
  2.times {relay_verilog}
  reset.intVal = 0
end

Version data entries

2 entries across 1 versions & 1 rubygems

Version	Path
ruby-vpi-13.0.0	samp/counter/counter_rspec_design.rb
ruby-vpi-13.0.0	samp/counter/counter_xunit_design.rb