%#`include "<%= options[:top] %>"

`timescale 1ns/1ns

// 0 - Data
// 1 - Reserved 
//
// 0 - Drive
//
// 0 - Compare
//
// 0 - Force data 0
// 1 - Force data 1
module pin_driver(error, pin, sync);
  parameter init_drive = 2; // Which means don't drive initially, set to 0 or 1 to drive

  output reg error;
  inout pin;
  input sync;

  reg [1:0] data = 0;
  reg [1:0] force_data = 0;
  reg compare = 0;
  reg drive = 0;
  reg capture = 0;
  //reg [1023:0] memory = 0;
  reg [127:0] memory = 0;
  reg [127:0] memory_reversed = 0;
  reg [127:0] sync_memory = 0;

  wire drive_data = force_data[0] ? 0 : (force_data[1] ? 1 : data[0]);

  assign pin = drive ? drive_data : 1'bz;

  // Debug signal to show the expected data in the waves
  wire expect_data = compare ? data[0] : 1'bz;

  always @(*) begin
    error = (compare && !capture) ? (pin == data[0] ? 0 : 1) : 0;
  end

  always @(posedge capture) begin
    if (sync == 1) begin
      sync_memory[127:1] <= sync_memory[126:0];
      sync_memory[0] <= pin;
    end else begin
      memory[127:1] <= memory[126:0];
      memory[0] <= pin;
      memory_reversed[126:0] <= memory_reversed[127:1];
      memory_reversed[127] <= pin;
    end
  end

  initial begin
    if (init_drive == 1) begin
      drive = 1;
      data[0] = 1;
    end else if (init_drive == 0) begin
      drive = 1;
      data[0] = 0;
    end
  end

endmodule

module pin_drivers(errors, <%= dut.rtl_pins.map { |n, p, o| "#{p.id}_o" unless p.tie_off }.compact.join(', ') %>);

% dut.rtl_pins.each do |name, pin, options|
%   unless pin.tie_off
  output <%= pin.id %>_o;
%   end
% end

% dut.rtl_pins.each do |name, pin, options|
%   unless pin.tie_off
  wire <%= pin.id %>_err;
%   end
% end

  output reg [31:0] errors = 0;
  reg sync = 0;

  always @(

% dut.rtl_pins.each_with_index do |(name, pin, options), i|
%   unless pin.tie_off
%     if i == 0
    posedge <%= pin.id %>_err
%     else
    or posedge <%= pin.id %>_err
%     end
%   end
% end
  ) begin
    errors[31:0] = errors[31:0] + 1;
  end

% dut.rtl_pins.each do |name, pin, options|
%   unless pin.tie_off
  pin_driver <%= pin.driving? ? "#(#{pin.value}) " : '' %><%= pin.id %>(.pin(<%= pin.id %>_o), .error(<%= pin.id %>_err), .sync(sync));
%   end 
% end

endmodule


module debug(errors);

  input [31:0] errors;

  reg [1023:0] pattern = 0;
  reg [1023:0] comments = 0;

  reg handshake;

endmodule

module origen;

  reg finish = 0;

% dut.rtl_pins.each do |name, pin, options|
%   unless pin.tie_off
  wire <%= pin.id %>;
%   end
% end

  wire [31:0] errors;

  pin_drivers pins (
% dut.rtl_pins.each_with_index do |(name, pin, options), i|
%   unless pin.tie_off
    .<%= pin.id %>_o(<%= pin.id %>),
%   end
% end
    .errors(errors)
  );

  // Create wires to tie off DUT signals, initially this was done by hardcoded values when instantiating
  // below, however the simulator didn't like that if the target pin was defined as an inout
% dut.rtl_pins.each do |name, pin, options|
%   if options[:group]
%     if pin.group_index == 0
%       if pin.primary_group.tie_off
  wire [<%= pin.primary_group.size - 1 %>:0] <%= pin.rtl_name %>;
  assign <%= pin.rtl_name %> = <%= "#{pin.primary_group.size}'b#{pin.tie_off.to_s * pin.primary_group.size}" %>;
%       end
%     end
%   else
%     if pin.tie_off
  wire <%= pin.rtl_name %>;
  assign <%= pin.rtl_name %> = 1'b<%= pin.tie_off %>;
%     end
%   end
% end


  // Instantiate the DUT
  <%= options[:top].sub(/\..*/, '') %> dut (
% dut.power_pins.each do |name, pin, options|
%   unless pin.tie_off
    .<%= pin.id %>(<%= pin.id %>),
%   end
% end
% dut.ground_pins.each do |name, pin, options|
%   unless pin.tie_off
    .<%= pin.id %>(<%= pin.id %>),
%   end
% end
% dut.rtl_pins.each_with_index do |(name, pin, options), i|
%   if options[:group]
%     if pin.group_index == 0
%       if pin.primary_group.tie_off
    .<%= pin.rtl_name %>(<%= pin.rtl_name %>)<%= i == (dut.rtl_pins.size - 1) ? '' : ',' %>
%       else
    .<%= pin.rtl_name %>({
%         pin.primary_group.each_with_index do |pin, i|
      <%= pin.id %><%= i == (pin.primary_group.size - 1) ? '' : ',' %>
%         end
    })<%= i == (dut.rtl_pins.size - 1) ? '' : ',' %>
%       end
%     end
%   else
    .<%= pin.rtl_name %>(<%= pin.tie_off ? pin.rtl_name : pin.id %>)<%= i == (dut.rtl_pins.size - 1) ? '' : ',' %>
%   end
% end
  );

  debug debug (
    .errors(errors)
  );

% if options[:vendor] == :icarus  
  initial
  begin
    $dumpfile("dut.vcd");
    $dumpvars(0,origen);
  end
% end
    
  always @(posedge finish) begin
    $finish(2);
  end

%  Array(options[:incl]).each do |f|
  `include "<%= "#{f}" %>"
%  end

endmodule