Contents

# Ruby prototype of the design under test's Verilog implementation.
def feign!
  if rw.low?
    reg           = register.memoryWord_a[rdReg.intVal]
    outBus.intVal = reg.intVal

  elsif enable.high?
    reg           = register.memoryWord_a[wtReg.intVal]
    reg.intVal    = inBus.intVal
  end
end

Version data entries

4 entries across 4 versions & 1 rubygems

Version	Path
ruby-vpi-17.0.0	samp/register_file/register_file_proto.rb
ruby-vpi-18.0.0	samp/register_file/register_file_proto.rb
ruby-vpi-18.0.1	samp/register_file/register_file_proto.rb
ruby-vpi-18.0.2	samp/register_file/register_file_proto.rb