Contents

<% clock = aModuleInfo.clock_port.name rescue "YOUR_CLOCK_SIGNAL_HERE" %>
# Simulates the design under test for one clock cycle.
def DUT.cycle!
  <%= clock %>.high!
  advance_time

  <%= clock %>.low!
  advance_time
end

<% reset = aModuleInfo.reset_port.name rescue "YOUR_RESET_SIGNAL_HERE" %>
# Brings the design under test into a blank state.
def DUT.reset!
  <%= reset %>.high!
  cycle!
  <%= reset %>.low!
end

Version data entries

3 entries across 3 versions & 1 rubygems

Version	Path
ruby-vpi-20.0.0	bin/generate/design.rb
ruby-vpi-21.1.0	bin/generate/design.rb
ruby-vpi-21.0.0	bin/generate/design.rb