# File lib/ruby-vpi/verilog_parser.rb, line 52
52:     def initialize aDecl
53:       @decl = aDecl.strip
54: 
55:       @decl =~ %r{module\s+(\w+)\s*(?:\#\((.*?)\))?\s*\((.*?)\)\s*;}m
56:       @name, paramDecls, portDecls = $1, $2, $3
57: 
58:       @parameters =
59:         if paramDecls =~ %r{\bparameter\b(.*)$}
60:           $1.split(',').map! do |decl|
61:             Parameter.new decl
62:           end
63:         else
64:           []
65:         end
66: 
67:       @ports = portDecls.split(',').map! do |decl|
68:         Port.new decl
69:       end
70:     end