Ruby-VPI http://ruby-vpi.rubyforge.org Ruby-VPI is a Ruby interface to IEEE 1364-2005 Verilog VPI and a platform for unit testing, rapid prototyping, and systems integration of Verilog modules through Ruby. It lets you create complex Verilog test benches easily and wholly in Ruby. Version 18.0.0 released http://ruby-vpi.rubyforge.org/doc/history.html#a18.0.0 http://ruby-vpi.rubyforge.org/doc/history.html#a18.0.0 <h1 id="18.0.0">Version 18.0.0 (2007-07-31)</h1> <p>This release restores support for Synopsys VCS and Cadence NC-Sim, improves portability and performance, and enhances the VPI abstraction layer.</p> <h2>Thanks</h2> <ul> <li>Calvin Wong discovered <a href="http://rubyforge.org/forum/message.php?msg_id=25691">how to bypass the following error</a> emitted by Synopsys VCS when loading the Ruby-VPI shared object file. <pre> Could not open library specified in -load option obj/vcs obj/vcs: undefined symbol: vpi_put_data </pre></li> </ul> <h2>Caution</h2> <ul> <li><a href="http://www.swig.org/">SWIG</a> is now required in order to compile and install Ruby-VPI.</li> </ul> <ul> <li><code class="code"><span style="color:#036; font-weight:bold">Vpi</span>::<span style="color:#036; font-weight:bold">Handle</span>.put_value</code> no longer checks whether the value written matches the value read back after writing because that only works when there is no VPI delay associated with the write.</li> </ul> <ul> <li>When <code class="code"><span style="color:#036; font-weight:bold">Vpi</span>::<span style="color:#036; font-weight:bold">Handle</span>.put_value</code> is used to write a value to a wire (VpiNet), it now <em>forces</em> the value. This is done to ensure portability: <p>Synopsys VCS and Cadence NC-Sim forget the value written to a wire during the next simulation time step, whereas Mentor Modelsim and GPL Cver remember the value (thereby treating wires as registers).</p> <p>Note that you have to release a forced value (using <code class="code"><span style="color:#036; font-weight:bold">Vpi</span>::<span style="color:#036; font-weight:bold">Handle</span>.release_value</code>) on a wire after writing to the wire if you want the design under test have the ability to update the value of the wire later on:</p> <pre class="code"> your_wire.intVal = <span style="color:#00D; font-weight:bold">15</span> your_wire.release_value advance_time <span style="color:#888"># let the Verilog DUT modify your_wire</span> </pre> <p>In addition, you can check if a wire has a forced value using the <code class="code"><span style="color:#036; font-weight:bold">Vpi</span>::<span style="color:#036; font-weight:bold">Handle</span>.value_forced?</code> method.</p></li> </ul> <ul> <li>If the format is not specified, <code class="code"><span style="color:#036; font-weight:bold">Vpi</span>::<span style="color:#036; font-weight:bold">Handle</span>.get_value</code> now assumes that you want to read the value in VpiIntVal format (because this is the most common case).</li> </ul> <ul> <li>The definition of &#8220;Derivatives&#8221; has been reworded for clarity in the <a href="readme.html#intro.license">project license</a>.</li> </ul> <h2>Repairs</h2> <ul> <li>Synopsys VCS and Cadence NC-Sim simulators now correctly load Ruby-VPI. Also, the 64-bit versions of these simulators are now supported.</li> </ul> <h2>Improvements</h2> <ul> <li>Added &#8220;force_value&#8221;, &#8220;release_value&#8221;, and &#8220;value_forced?&#8221; methods to the <code class="code"><span style="color:#036; font-weight:bold">Vpi</span>::<span style="color:#036; font-weight:bold">Handle</span></code> class.</li> </ul> <ul> <li><code class="code"><span style="color:#036; font-weight:bold">Vpi</span>::<span style="color:#036; font-weight:bold">Handle</span>.put_value</code> now tries to automatically detect the format of the value to be written. As a result, you can now write <code class="code">your_handle.put_value <span style="color:#00D; font-weight:bold">35</span></code> in lieu of writing <code class="code">your_handle.intVal = <span style="color:#00D; font-weight:bold">35</span></code>.</li> </ul> <ul> <li><code class="code"><span style="color:#036; font-weight:bold">Vpi</span>::<span style="color:#036; font-weight:bold">Handle</span>.inspect</code> now shows the hexStrVal of the handle (because it is a common case to want to see a handle&#8217;s logic value along with its other information).</li> </ul> <ul> <li>Added method caching (memoizing) for VPI property accesses on handles.</li> </ul> Tue, 31 Jul 2007 00:00:00 PDT Version 17.0.0 released http://ruby-vpi.rubyforge.org/doc/history.html#a17.0.0 http://ruby-vpi.rubyforge.org/doc/history.html#a17.0.0 <h1 id="17.0.0">Version 17.0.0 (2007-07-22)</h1> <p>This release makes the Ruby-VPI testing framework more lightweight by reducing the number of files and parameters involved.</p> <h2>Caution</h2> <ul> <li>The <strong>generate_test.rb</strong> and <strong>convert.rb</strong> executables have been replaced by a single <strong>ruby-vpi</strong> executable to avoid name conflicts with other software. They are now accessed using the <pre>ruby-vpi generate</pre> and <pre>ruby-vpi convert</pre> commands respectively.</li> </ul> <ul> <li>The <tt>--name</tt> parameter has been removed from the automated test generator. Similarly, you can no longer insert an arbitrary name in a test&#8217;s file names (see the <a href="manual.html#Do_not_rename_generated_files">user manual</a> for details).</li> </ul> <ul> <li>The <code class="code"><span style="color:#036; font-weight:bold">DEBUG</span></code> environment variable, which controls wether the test runner starts the interactive debugger, has been renamed to <code class="code"><span style="color:#036; font-weight:bold">DEBUGGER</span></code>.</li> </ul> <ul> <li>The <code class="code"><span style="color:#036; font-weight:bold">SIMULATOR_TARGET</span></code> and <code class="code"><span style="color:#036; font-weight:bold">SIMULATOR_INCLUDES</span></code> parameters have been eliminated from test runners. The former is detected automatically. As for the latter, you can specify paths to directories in the <code class="code"><span style="color:#036; font-weight:bold">SIMULATOR_SOURCES</span></code> parameter instead.</li> </ul> <ul> <li>The <tt>bench.rb</tt> and <tt>bench.v</tt> files of a generated test are (1) no longer generated by the test generator and (2) are now ignored. You must move the functionality provided by these files into <tt>design.rb</tt> and your Verilog module&#8217;s source file respectively.</li> </ul> <ul> <li>The <tt>design.rb</tt> and <tt>proto.rb</tt> files are now loaded into a separate namespace (Ruby module). For example, if the Verilog module under test has the name &#8220;counter&#8221; and the <tt>design.rb</tt> file defines a class named &#8220;Foo&#8221;, then that class will be accessible as &#8220;Counter::Foo&#8221;.</li> </ul> <ul> <li>The global <code class="code"><span style="color:#036; font-weight:bold">Vpi</span>::simulate</code> method has been replaced by the <code class="code">cycle!</code> method in the <tt>design.rb</tt> file.</li> </ul> <ul> <li>The <code class="code">simulate!</code> method in the <tt>proto.rb</tt> file has been renamed to <code class="code">feign!</code> for accuracy.</li> </ul> <ul> <li>The <code class="code"><span style="color:#036; font-weight:bold">RubyVpi</span></code> module has been renamed to <code class="code"><span style="color:#036; font-weight:bold">RubyVPI</span></code>.</li> </ul> <ul> <li>RSpec &gt;= 1.0.0 is now required by Ruby-VPI.</li> </ul> <ul> <li>The <a href="readme.html#intro.license">project license</a> has been further simplified.</li> </ul> <h2>Repairs</h2> <ul> <li>Restored support for Enumerable methods in <code class="code"><span style="color:#036; font-weight:bold">Vpi</span>::<span style="color:#036; font-weight:bold">Handle</span></code>.</li> </ul> <ul> <li>The specification now begins to execute at simulation time 0. Previously it began at simulation time 1.</li> </ul> <h2>Improvements</h2> <ul> <li>The <tt>bench.rb</tt> and <tt>bench.v</tt> files of a generated test have been eliminated! <p>One important benefit is that the Ruby interface to the Verilog module under test is now a direct reference, whereas previously it was an <em>indirect</em> reference (it pointed to the Verilog module defined in <tt>bench.v</tt>, which in turn wrapped around the actual Verilog module under test).</p> <p>As a result, you can now access the internals of the Verilog module under test by simply calling methods on the Ruby interface, as you would naturally expect to be the case.</p></li> </ul> <ul> <li>The &#8220;a&#8221; accessor, which returns an <em>array</em> of child handles, has been added to <a href="manual.html#tbl:accessors">the method naming format</a> for accessing child handles.</li> </ul> <ul> <li>All parameter objects in the Verilog module under test are automatically made available as constants. For example, if the Verilog module under test has the name <code class="code">counter</code> and has a parameter object named <code class="code"><span style="color:#036; font-weight:bold">WIDTH</span></code>, then you can access the integer value of that parameter using <code class="code"><span style="color:#036; font-weight:bold">Counter</span>::<span style="color:#036; font-weight:bold">WIDTH</span></code>.</li> </ul> <ul> <li>The automated test generator now tries to automatically detect the clock and reset signal from Verilog module declarations.</li> </ul> <ul> <li>The automated test generator now supports Verilog 95 style module declarations.</li> </ul> <ul> <li>Exceptions are now raised when you try to write to a read-only VPI property, such as <code class="code"><span style="color:#036; font-weight:bold">VpiName</span></code>.</li> </ul> <ul> <li>Added <code class="code">high?</code>, <code class="code">high!</code>, <code class="code">low?</code>, and <code class="code">low!</code> methods to the <code class="code"><span style="color:#036; font-weight:bold">Vpi</span>::<span style="color:#036; font-weight:bold">Handle</span></code> class.</li> </ul> <ul> <li>Revised the user manual by removing unnecessary sections and adding newer material from my master&#8217;s thesis.</li> </ul> <h2>Contributions</h2> <ul> <li>Added Jacinto Shy II&#8217;s <a href="http://jacintoshy.blogspot.com/2007/05/hacking-verilog-with-ruby-part-2.html">register file example</a> to Ruby-VPI. It can be found in <tt>samp/register_file/</tt>.</li> </ul> Sun, 22 Jul 2007 00:00:00 PDT Version 16.0.1 released http://ruby-vpi.rubyforge.org/doc/history.html#a16.0.1 http://ruby-vpi.rubyforge.org/doc/history.html#a16.0.1 <h1 id="16.0.1">Version 16.0.1 (2007-05-27)</h1> <p>This release restores support for installation on Mac <span class="caps">OS X</span>.</p> <h2>Thanks</h2> <ul> <li>Mark Thompson <a href="http://rubyforge.org/tracker/index.php?func=detail&#38;aid=11125&#38;group_id=1339&#38;atid=5281">reported and solved</a> the problem.</li> </ul> <h2>Repairs</h2> <ul> <li>Shared-object files have a file extension of <tt>.so</tt> in Linux and <tt>.bundle</tt> on Mac <span class="caps">OS X</span>. Previously, only the Linux file extension was supported.</li> </ul> Sun, 27 May 2007 00:00:00 PDT