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<title>new (VerilogParser::Module::Port)</title>
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<pre><span class="ruby-comment cmt"># File lib/ruby-vpi/verilog_parser.rb, line 47</span>
<span class="ruby-keyword kw">def</span> <span class="ruby-identifier">initialize</span> <span class="ruby-identifier">aDecl</span>, <span class="ruby-identifier">aModule</span>
<span class="ruby-ivar">@decl</span> = <span class="ruby-identifier">aDecl</span>
<span class="ruby-ivar">@name</span> = <span class="ruby-identifier">aDecl</span>.<span class="ruby-identifier">scan</span>(<span class="ruby-regexp re">/\S+/</span>).<span class="ruby-identifier">last</span>
<span class="ruby-identifier">parser</span> = <span class="ruby-node">/\b(input|output|inout)\b[^;]*\b#{@name}\b/</span><span class="ruby-identifier">m</span>
<span class="ruby-identifier">aDecl</span> <span class="ruby-operator">=~</span> <span class="ruby-identifier">parser</span> <span class="ruby-operator">||</span> <span class="ruby-identifier">aModule</span>.<span class="ruby-identifier">body</span> <span class="ruby-operator">=~</span> <span class="ruby-identifier">parser</span>
<span class="ruby-ivar">@type</span> = <span class="ruby-identifier">$1</span>
<span class="ruby-keyword kw">end</span></pre>
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