# File lib/ruby-vpi/verilog_parser.rb, line 47
47:       def initialize aDecl, aModule
48:         @decl = aDecl
49:         @name = aDecl.scan(/\S+/).last
50: 
51:         parser = /\b(input|output|inout)\b[^;]*\b#{@name}\b/m
52:         aDecl =~ parser || aModule.body =~ parser
53:         @type = $1
54:       end