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## Origen Export

This page shows how to create static read-only Ruby files from
models created by importing 3rd party data (e.g. IP-XACT). The Ruby files can then be
used for day-day running of your application and this will significantly improve
the boot up speed vs. re-importing the data every time.

The Ruby files can be periodically refreshed as new versions of the master
data are released.

The user only need provide the output path where they want the
Ruby files to be written.

### Implementation

Here is an example of how to create the static Ruby files.

~~~ruby
$dut.to_origen(path: "#{Origen.root}/output/exported")
~~~

### Output

At the output path the following files are created:

* top_level.rb: The top-level object, this is the one that should be instantiated

~~~ruby
# This file is created by Origen, CrossOrigen::OrigenFormat#export, and is read-only
require_relative 'sub_blocks'
module CrossOrigen
  module Test
    class DUT
      include Origen::Model

      def initialize(options = {})
        sub_block :atx, base_address: 0xDEADBEEF, class_name: 'ATX'
        sub_block # ...
      end
    end
  end
end
~~~

* sub_blocks.rb: include file for the sub_block class files

~~~ruby
# This file is created by Origen, CrossOrigen::OrigenFormat#export, and is read-only
require_relative 'import/atx.rb'
require_relative # ...
~~~

* import/\<sub_block\>.rb: models the individual sub_block object

~~~ruby
# -*- encoding : utf-8 -*-
# This file is created by Origen, CrossOrigen::OrigenFormat#export, and is read-only.
# If you need to make changes, re-open the class
module CrossOrigen
  module Test
    class DUT
      class ATX # rubocop:disable ClassLength
        include Origen::Model

        def initialize(options = {})
          instantiate_registers(options)
        end

        # rubocop:disable LineLength
        # rubocop:disable StringLiterals
        def instantiate_registers(options = {}) # rubocop:disable MethodLength
          # ** MGATE Clock Divider Register **
          # The MCLKDIV register is used to divide down the frequency of the HBOSCCLK input. If the MCLKDIV
          # register is set to value "N", then the output (beat) frequency of the clock divider is OSCCLK / (N+1). The
          # resulting beats are, in turn, counted by the PTIMER module to control the duration of Flash high-voltage
          # operations.
          reg :mclkdiv, 0x0, size: 16 do |reg|
            # **Oscillator (Hi)** - Firmware FMU clk source selection. (Note that in addition to this firmware-controlled bit, the
            # FMU clock source is also dependent on test and power control discretes).
            # 
            # 0 | FMU clock is the externally supplied bus clock ipg_clk
            # 1 | FMU clock is the internal oscillator from the TFS hardblock
            reg.bit 15, :osch, reset: 0b1, access: :rw
            # ...
          end
          # ...
        end
      end
    end
  end
end
~~~

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