help:
  new:
    short: Generate a new project in PATH
    long:  |
      Creates a new chip project in PATH.
   
      Example: ecic new my_project

      This creates a new ECIC project in ./my_project
  completion:
    short: Print words for auto-completion
    long:   |
      Example:

        ecic completion

      Prints words for TAB auto-completion.

      Examples:

        ecic completion
        ecic completion generate
        ecic completion generate design

      To enable TAB auto-completion, add the following to your profile:

        eval $(ecic completion script)

      Auto-completion example usage:

        ecic [TAB]
        ecic generate [TAB]
        ecic generate design [TAB]
        ecic generate design --[TAB]      
      
    script:
      short: Generate script that can be eval to setup auto-completion      
      long: |
        To use, add the following to your ~/.bashrc or ~/.profile

          eval $(ecic completion script)      

  generate:
    short: Generate new testbenches, RTL modules, tests etc.!
    testbench:
      short: Create a new testbench
      long: |
        Create a new VHDL, SystemVerilog or UVM testbench.
        The testbench type MUST be defined with the --type option.

        Example: ecic generate testbench my_tb --type=uvm --verbose

        This creates a new UVM testbench called 'my_tb' in ./src/testbench/my_tb and prints info along the way
        
    library:
      short: Create a new library
      long: |
            Create a new VHDL/SystemVerilog library.
            
            Example: ecic generate library lib1 lib2 lib3...

            This creates the given libraries in the ./src/design/ directory of 
            your project and adds the libraries to ./src/config/libraries.rb
            
    design:
      short: Create a new RTL design
      long: |
            Create a new VHDL/SystemVerilog design.
            
            Example: ecic generate design --type=vhdl --library=some_lib design1 sub_block/design2

            This creates the component, entity and architecture files for two designs called 'design1' and 'design2'.
            An optional types and constants definition file may also be created for each design.
            The files for 'design1' will be placed under 'src/design/some_lib' whereas the files for 'design2'
            will be placed in 'src/design/some_lib/sub_block'.
            
            The RTL files are automatically added to the project and the given library will be created and added as well if needed.