| Class | OutputInfo |
| In: |
bin/generate_test.rb
|
| Parent: | Object |
Holds information about the output destinations of a parsed Verilog module.
| RUBY_EXT | = | '.rb' |
| VERILOG_EXT | = | '.v' |
| RUNNER_EXT | = | '.rake' |
| SPEC_FORMATS | = | [:RSpec, :UnitTest, :Generic] |
| benchSuffix | [R] | |
| designClassName | [R] | |
| designName | [R] | |
| designPath | [R] | |
| designSuffix | [R] | |
| protoClassName | [R] | |
| protoName | [R] | |
| protoPath | [R] | |
| protoSuffix | [R] | |
| rubyBenchName | [R] | |
| rubyBenchPath | [R] | |
| rubyVpiPath | [R] | |
| runnerName | [R] | |
| runnerPath | [R] | |
| runnerSuffix | [R] | |
| specClassName | [R] | |
| specFormat | [R] | |
| specName | [R] | |
| specPath | [R] | |
| specSuffix | [R] | |
| suffix | [R] | |
| testName | [R] | |
| verilogBenchName | [R] | |
| verilogBenchPath | [R] |