Sha256: 19f3b06b76dc439918ded30fcd67827de50bccefa1316a766200d77b447cfbe5
Contents?: true
Size: 830 Bytes
Versions: 17
Compression:
Stored size: 830 Bytes
Contents
library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
Version data entries
17 entries across 17 versions & 1 rubygems